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PXI-8232
該設(shè)備還使用TRIG1啟動(dòng)預(yù)觸發(fā)的DAQ操作。在大多數(shù)預(yù)觸發(fā)應(yīng)用程序中，TRIG1由軟件觸發(fā)器生成。有關(guān)在預(yù)觸發(fā)DAQ操作中使用TRIG1和TRIG2的完整說明，請(qǐng)參閱TRIG2信號(hào)說明。TRIG2信號(hào)任何PFI引腳均可接收TRIG2信號(hào)作為輸入，該信號(hào)可作為PFI1/TRIG2引腳的輸出。TRIG2與DAQ序列的關(guān)系見圖4-10。作為輸入，TRIG2配置為邊緣檢測(cè)模式。您可以選擇任何PFI引腳作為TRIG2的源，并為上升沿或下降沿配置極性選擇。TRIG2的選定邊緣啟動(dòng)預(yù)觸發(fā)DAQ序列的后觸發(fā)階段。在預(yù)觸發(fā)模式下，TRIG1信號(hào)啟動(dòng)數(shù)據(jù)采集。掃描計(jì)數(shù)器（SC）指示識(shí)別TRIG2之前的小掃描次數(shù)。SC減至零后，將加載要采集的觸發(fā)后掃描數(shù)，同時(shí)繼續(xù)采集。如果在SC遞減為零之前斷言TRIG2，則設(shè)備忽略TRIG2。收到TRIG2的選定邊緣后，設(shè)備獲取固定數(shù)量的上升邊緣極性下降邊緣極性t w t w=10 ns小t w t w=25-50 ns第4章連接信號(hào)©National Instruments Corporation 4-21 NI PCI-6110/6111用戶手冊(cè)掃描和采集停止。此模式在接收TRIG2之前和之后都會(huì)獲取數(shù)據(jù)。作為輸出，TRIG2在預(yù)觸發(fā)采集序列中反映后觸發(fā)，即使另一個(gè)PFI正在外部觸發(fā)采集。TRIG2不用于后觸發(fā)數(shù)據(jù)采集。輸出為有源高脈沖，脈沖寬度為25至50 ns。該輸出在啟動(dòng)時(shí)設(shè)置為高阻抗。圖4-13和4-14顯示了TRIG2的定時(shí)要求。

The device also uses TRIG1 to initiate pretriggered DAQ operations. In most pretriggered applications, TRIG1 is generated by a software trigger. Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation. TRIG2 Signal Any PFI pin can receive as an input the TRIG2 signal, which is available as an output on the PFI1/TRIG2 pin. Refer to Figure 4-10 for the relationship of TRIG2 to the DAQ sequence. As an input, TRIG2 is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge. The selected edge of TRIG2 initiates the posttriggered phase of a pretriggered DAQ sequence. In pretriggered mode, the TRIG1 signal initiates the data acquisition. The scan counter (SC) indicates the minimum number of scans before TRIG2 can be recognized. After the SC decrements to zero, it is loaded with the number of posttrigger scans to acquire while the acquisition continues. The device ignores TRIG2 if it is asserted prior to the SC decrementing to zero. After the selected edge of TRIG2 is received, the device acquires a fixed number Rising-edge polarity Falling-edge polarity t w t w = 10 ns minimum t w t w = 25-50 ns Chapter 4 Connecting Signals © National Instruments Corporation 4-21 NI PCI-6110/6111 User Manual of scans and the acquisition stops. This mode acquires data both before and after receiving TRIG2. As an output, TRIG2 reflects the posttrigger in a pretriggered acquisition sequence even if another PFI is externally triggering the acquisition. TRIG2 is not used in posttriggered data acquisition. The output is an active high pulse with a pulse width of 25 to 50 ns. This output is set to high impedance at startup. Figures 4-13 and 4-14 show the timing requirements for TRIG2.