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NI PCI-6517(32路漏極輸出)
外部時鐘采集，NI-DAQ不知道何時獲取后一個點，因此必須提供三個額外的脈沖。CONVERT*信號任何PFI引腳都可以接收CONVERT*信號作為輸入，該信號可作為PFI2/CONVERT*引腳上的輸出。CONVERT*與DAQ序列的關(guān)系見圖4-9和4-10。作為輸入，CONVERT*在邊緣檢測模式下配置。您可以選擇任何PFI引腳作為轉(zhuǎn)換*的源，并配置上升沿或下降沿的極性選擇。CONVERT*的選定邊緣啟動A/D轉(zhuǎn)換。作為輸出，CONVERT*反映連接到ADC的實際轉(zhuǎn)換脈沖，即使另一個PFI在外部生成轉(zhuǎn)換。輸出為有效低脈沖，脈沖寬度為50至100 ns。該輸出在啟動時設(shè)置為高阻抗。圖4-17和4-18顯示了轉(zhuǎn)換*的計時要求。圖4-17：。CONVERT*輸入信號定時上升沿極性下降沿極性t w t w=10 ns小值4章連接信號©National Instruments Corporation 4-25 NI PCI-6110/6111用戶手冊圖4-18。CONVERT*輸出信號定時ADC切換到保持模式，距離選定邊緣20 ns以內(nèi)。該保持模式延遲時間是溫度的函數(shù)，在一次轉(zhuǎn)換到下一次轉(zhuǎn)換時不會變化。除非您選擇一些外部源，否則NI PCI-6110/6111上的SI2通常會生成CONVERT*。計數(shù)器由STARTSCAN信號啟動，繼續(xù)并重新加載，直到掃描完成。然后，它重新加載自己，為下一個STARTSCAN脈沖做好準備。由內(nèi)部或外部CONVERT*信號生成的A/D轉(zhuǎn)換被禁止，除非它們發(fā)生在DAQ序列中。DAQ序列中發(fā)生的掃描可通過硬件（AIGATE）信號或軟件命令寄存器門進行選通。AIGATE信號任何PFI引腳都可以接收AIGATE信號作為輸入，AIGATE信號不能作為輸入/輸出連接器上的輸出。AIGATE信號可以在DAQ序列中屏蔽掃描。您可以在電平檢測或邊緣檢測模式下配置您選擇作為AIGATE信號源的PFI引腳。您可以將PFI引腳的極性選擇配置為激活高電平或激活低電平。在液位檢測模式下，如果AIGATE處于激活狀態(tài)，STARTSCAN信號將被屏蔽，并且不會發(fā)生掃描。在邊緣檢測模式下，一條活動邊緣禁用STARTSCAN信號，二條活動邊緣啟用STARTSCAN。AIGATE既不能停止正在進行的掃描，也不能繼續(xù)以前的選通關(guān)閉掃描。一旦掃描開始，AIGATE在下一次掃描開始之前不會關(guān)閉轉(zhuǎn)換，相反，如果

externally clocked acquisition, NI-DAQ does not know when the last point is taken, so you must provide the three extra pulses. CONVERT* Signal Any PFI pin can receive as an input the CONVERT* signal, which is available as an output on the PFI2/CONVERT* pin. Refer to Figures 4-9 and 4-10 for the relationship of CONVERT* to the DAQ sequence. As an input, CONVERT* is configured in the edge-detection mode. You can select any PFI pin as the source for CONVERT* and configure the polarity selection for either rising or falling edge. The selected edge of CONVERT* initiates an A/D conversion. As an output, CONVERT* reflects the actual convert pulse that is connected to the ADC, even if another PFI is externally generating the conversions. The output is an active low pulse with a pulse width of 50 to 100 ns. This output is set to high-impedance at startup. Figures 4-17 and 4-18 show the timing requirements for CONVERT*. Figure 4-17. CONVERT* Input Signal Timing Rising-edge polarity Falling-edge polarity t w t w = 10 ns minimum Chapter 4 Connecting Signals © National Instruments Corporation 4-25 NI PCI-6110/6111 User Manual Figure 4-18. CONVERT* Output Signal Timing The ADC switches to hold mode within 20 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next. The SI2 on the NI PCI-6110/6111 normally generates CONVERT* unless you select some external source. The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished. It then reloads itself in preparation for the next STARTSCAN pulse. A/D conversions generated by either an internal or external CONVERT* signal are inhibited unless they occur within a DAQ sequence. Scans occurring within a DAQ sequence may be gated by either the hardware (AIGATE) signal or software command register gate. AIGATE Signal Any PFI pin can receive as an input the AIGATE signal, which is not available as an output on the I/O connector. The AIGATE signal can mask off scans in a DAQ sequence. You can configure the PFI pin you select as the source for the AIGATE signal in either the level-detection or edge-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low. In the level-detection mode if AIGATE is active, the STARTSCAN signal is masked off and no scans can occur. In the edge-detection mode, the first active edge disables the STARTSCAN signal, and the second active edge enables STARTSCAN. AIGATE can neither stop a scan in progress nor continue a previously gated-off scan. Once a scan has started, AIGATE does not gate off conversions until the beginning of the next scan and, conversely, if