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VMIVME-333-000132-C
提供一個(gè)可編程看門狗定時(shí)器（WDT），如果軟件完整性出現(xiàn)故障，該定時(shí)器可用于重置系統(tǒng)。WDT控制狀態(tài)寄存器（WCSR）WDT由WDT控制狀態(tài)寄存器（WCSR）控制和監(jiān)控，該寄存器位于BAR2中地址的偏移量0x08處。該寄存器中的位映射如下：“WDT超時(shí)選擇”字段用于選擇看門狗計(jì)時(shí)器的超時(shí)值，如下所示：“SERR/RST選擇”位用于選擇WDT是在本地PCI總線上生成SERR#還是系統(tǒng)重置。如果該位設(shè)置為“0”，WDT將生成系統(tǒng)復(fù)位。否則，WDT將激活本地PCI總線SERR信號(hào)。“WDT Enable”（WDT啟用）位用于啟用看門狗定時(shí)器功能。該位必須設(shè)置為“1”，以使看門狗定時(shí)器正常工作。請(qǐng)注意，由于重置后所有寄存器默認(rèn)為零，因此重置后始終禁用看門狗計(jì)時(shí)器。重置后，應(yīng)用軟件必須重新啟用看門狗計(jì)時(shí)器，以便看門狗計(jì)時(shí)器繼續(xù)工作。啟用看門狗計(jì)時(shí)器后，應(yīng)用軟件必須在選定的超時(shí)時(shí)間內(nèi)刷新看門狗計(jì)時(shí)器，以防止產(chǎn)生重置或SERR。看門狗計(jì)時(shí)器是字段位讀或?qū)慡ERR/RST選擇WCSR[16]R/W WDT超時(shí)選擇WCSR[10..8]R/W WDT啟用WCSR[0]R/W所有這些位在系統(tǒng)重置后默認(rèn)為“0”。保留所有其他位。超時(shí)WCSR[10]WCSR[9]WCSR[8]135s 0 0 0 33.6s 0 1 2.1s 0 1 0 524ms 0 1 1 262ms 1 0 0 131ms 1 0 1 32.768ms 1 0 2.048ms 1 1 1 1 1

provide a programmable Watchdog Timer (WDT) which can be used to reset the system if software integrity fails. WDT Control Status Register (WCSR) The WDT is controlled and monitored by the WDT Control Status Register (WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of the bits in this register are as follows: The “WDT Timeout Select” field is used to select the timeout value of the Watchdog Timer as follows: The “SERR/RST Select” bit is used to select whether the WDT generates an SERR# on the local PCI bus or a system reset. If this bit is set to “0”, the WDT will generate a system reset. Otherwise, the WDT will make the local PCI bus SERR# signal active. The “WDT Enable” bit is used to enable the Watchdog Timer function. This bit must be set to “1” in order for the Watchdog Timer to function. Note that since all registers default to zero after reset, the Watchdog Timer is always disabled after a reset. The Watchdog Timer must be re-enabled by the application software after reset in order for the Watchdog Timer to continue to operate. Once the Watchdog Timer is enabled, the application software must refresh the Watchdog Timer within the selected timeout period to prevent a reset or SERR# from being generated. The Watchdog Timer is Field Bits Read or Write SERR/RST Select WCSR[16] R/W WDT Timeout Select WCSR[10..8] R/W WDT Enable WCSR[0] R/W All of these bits default to “0” after system reset. All other bits are reserved. Timeout WCSR[10] WCSR[9] WCSR[8] 135s 0 0 0 33.6s 0 0 1 2.1s 0 1 0 524ms 0 1 1 262ms 1 0 0 131ms 1 0 1 32.768ms 1 1 0 2.048ms 1 1 1