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VMIVME-7807
讀取此字段時，當(dāng)前計數(shù)值被鎖定并返回。有兩個
根據(jù)“Read”（讀?。┑脑O(shè)置確定如何鎖存計數(shù)的模式
鎖存WDT控制狀態(tài)寄存器（CSR2）中的“選擇”位。參見CSR2寄存器
有關(guān)這兩種模式的更多信息，請參閱說明。
定時器4電流計數(shù)寄存器（TMRCCR4）
定時器4的當(dāng)前計數(shù)可通過定時器4電流計數(shù)寄存器讀取
（TMRCCR4），位于BAR2中地址的偏移量0x28處。中的位映射
該登記冊如下：
讀取此字段時，當(dāng)前計數(shù)值被鎖定并返回。有兩個
根據(jù)“Read”（讀取）的設(shè)置確定如何鎖存計數(shù)的模式
鎖存WDT控制狀態(tài)寄存器（CSR2）中的“選擇”位。參見CSR2寄存器
有關(guān)這兩種模式的更多信息，請參閱說明。
定時器1 IRQ清除（T1IC）
定時器1 IRQ Clear（T1IC）寄存器用于清除定時器1引起的中斷。
寫入該寄存器（位于BAR2中地址的偏移量0x30處）會導(dǎo)致
定時器1的中斷被清除。也可以通過將“0”寫入
定時器控制狀態(tài)寄存器（CSR1）的相應(yīng)“定時器x導(dǎo)致IRQ”字段。
該寄存器僅寫，寫入的數(shù)據(jù)不相關(guān)。
定時器2 IRQ清除（T2IC）
定時器2 IRQ Clear（T2IC）寄存器用于清除定時器2引起的中斷。
寫入該寄存器（位于BAR2中地址的偏移量0x34處）會導(dǎo)致
定時器2的中斷被清除。也可以通過將“0”寫入
定時器控制狀態(tài)寄存器（CSR1）的相應(yīng)“定時器x導(dǎo)致IRQ”字段。
此寄存器為只寫寄存器，寫入的數(shù)據(jù)不相關(guān)。
定時器3 IRQ清除（T3IC）
定時器3 IRQ清除（T3IC）寄存器用于清除定時器3引起的中斷。
寫入該寄存器（位于BAR2中地址的偏移量0x38處）會導(dǎo)致
定時器3的中斷被清除。也可以通過將“0”寫入
定時器控制狀態(tài)寄存器（CSR1）的相應(yīng)“定時器x導(dǎo)致IRQ”字段。
此寄存器為只寫寄存器，寫入的數(shù)據(jù)不相關(guān)。
讀取或?qū)懭胱侄挝?br />計時器4計數(shù)TMRCCR4[31..0]R.O。

When this field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes. Timer 4 Current Count Register (TMRCCR4) The current count of Timer 4 may be read via the Timer 4 Current Count Register (TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits in this register are as follows: When this field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes. Timer 1 IRQ Clear (T1IC) The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2, causes the interrupt from Timer 1 to be cleared. This can also be done by writing a “0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1). This register is write only and the data written is irrelevant. Timer 2 IRQ Clear (T2IC) The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by Timer 2. Writing to this register, located at offset 0x34 from the address in BAR2, causes the interrupt from Timer 2 to be cleared. This can also be done by writing a “0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1). This register is write only and the data written is irrelevant. Timer 3 IRQ Clear (T3IC) The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by Timer 3. Writing to this register, located at offset 0x38 from the address in BAR2, causes the interrupt from Timer 3 to be cleared. This can also be done by writing a “0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1). This register is write only and the data written is irrelevant. Field Bits Read or Write Timer 4 Count TMRCCR4[31..0] R.O.