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VMIVME-7696-650
計(jì)時(shí)器4寬32位，從位于BAR2地址偏移量0x18處的計(jì)時(shí)器4加載計(jì)數(shù)寄存器（TMRLCR4）獲取其加載計(jì)數(shù)。該寄存器中的位映射如下：寫入該字段時(shí)，定時(shí)器4在定時(shí)器時(shí)鐘的下一個(gè)上升沿加載寫入值，無論定時(shí)器是啟用還是禁用。存儲(chǔ)在該寄存器中的值也會(huì)在計(jì)時(shí)器的終端計(jì)數(shù)（或超時(shí)）時(shí)自動(dòng)重新加載。計(jì)時(shí)器1和2當(dāng)前計(jì)數(shù)寄存器（TMRCCR12）計(jì)時(shí)器1和2的當(dāng)前計(jì)數(shù)可通過位于BAR2中地址偏移量0x20處的計(jì)時(shí)器1和2當(dāng)前計(jì)數(shù)寄存器（TMRCCR12）讀取。該寄存器中的位映射如下：讀取任一字段時(shí)，當(dāng)前計(jì)數(shù)值被鎖存并返回。根據(jù)WDT控制狀態(tài)寄存器（CSR2）中“讀取鎖存選擇”位的設(shè)置，有兩種模式可確定如何鎖存計(jì)數(shù)。有關(guān)這兩種模式的更多信息，請(qǐng)參閱CSR2寄存器說明。定時(shí)器3電流計(jì)數(shù)寄存器（TMRCCR3）定時(shí)器3的電流計(jì)數(shù)可通過位于BAR2地址偏移量0x24處的定時(shí)器3電流計(jì)數(shù)寄存器（TMRCCR3）讀取。該寄存器中的位映射如下：字段位讀取或?qū)懭胗?jì)時(shí)器4加載計(jì)數(shù)TMRLCR4[31..0]R/W字段位讀取或?qū)懭胗?jì)時(shí)器2計(jì)數(shù)TMRCCR12[31..16]R.O。計(jì)時(shí)器1計(jì)數(shù)TMRCCR12[15..0]R.O。

Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The mapping of bits in this register are as follows: When this field is written, Timer 4 is loaded with the written value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded on terminal count (or timeout) of the timer. Timer 1 & 2 Current Count Register (TMRCCR12) The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The mapping of bits in this register are as follows: When either field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes. Timer 3 Current Count Register (TMRCCR3) The current count of Timer 3 may be read via the Timer 3 Current Count Register (TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of bits in this register are as follows: Field Bits Read or Write Timer 4 Load Count TMRLCR4[31..0] R/W Field Bits Read or Write Timer 2 Count TMRCCR12[31..16] R.O. Timer 1 Count TMRCCR12[15..0] R.O.